The present invention is generally directed to methods and apparatuses for processing one or more microelectronic workpieces at elevated temperatures.
In the production of semiconductor integrated circuits and other microelectronic articles from microelectronic workpieces, such as semiconductor wafers, it is often necessary to provide multiple metal layers on a substrate to serve as interconnect metallization that electrically connects the various devices on the integrated circuit to one another. Traditionally, aluminum has been used for such interconnects, however, it is now recognized that copper metallization may be preferable. Copper interconnects can help alleviate many of the problems experienced in connection with the current aluminum technology.
The microelectronic fabrication industry has sought to use copper as the interconnect metallization by using a damascene and/or patterned plating electroplating process where holes (e.g., vias), trenches and other recesses are used to produce the desired copper patterns. In a typical damascene process, a dielectric layer is applied to the wafer and recesses are formed in the wafer. A metallic seed layer and barrier/adhesion layer are then disposed over the dielectric layer and into the recesses. The seed layer is used to conduct electrical current during a subsequent metal electroplating step. Preferably, the seed layer is a very thin layer of metal that can be applied using one of several processes. For example, the seed layer of metal can be applied using physical vapor deposition or chemical vapor deposition processes to produce a layer on the order of 1000 angstroms thick or less. The seed layer can also be formed of copper, gold, nickel, palladium, and most or all other metals. The seed layer conforms to the surface of the wafer, including the recesses, or other depressed or elevated device features.
In single copper electroplating damascene processes, two electroplating operations are generally employed. First, a copper layer is electroplated on the seed layer to form a blanket layer. The blanket layer fills the trenches or other recesses that define the horizontal interconnect wiring in the dielectric layer. The first blanket layer is then planarized (for example, by chemical-mechanical planarization) to remove those portions of the layer extending above the trenches, leaving the trenches filled with copper. A second dielectric layer is then provided to cover the wafer surface and recessed vias are formed in the second dielectric layer. The recessed vias are positioned to align with certain of the filled trenches. A second seed layer and a second copper blanket layer are applied to the surface of the second dielectric layer to fill the vias. The wafer is planarized again to remove copper extending above the level of the vias. The vias thus provide a vertical connection between the original horizontal interconnect layer and a subsequently applied horizontal interconnect layer. Electrochemical deposition of copper films has thus become an important process step in the manufacturing of high-performance microelectronic products.
Alternatively, the trenches and vias may be etched in the dielectric at the same time in what is commonly called a xe2x80x9cdual damascenexe2x80x9d process. These features are then processed, as above, with a barrier layer, a seed layer and a fill/blanket layer that fill the trenches and vias disposed at the bottoms of the trenches at the same time. The excess material is then polished, as above, to produce inlaid conductors.
The mechanical properties of the copper metallization can be quite important as the metal structures are formed. This is particularly true in connection with the impact of the mechanical properties of the copper metallization during chemical mechanical polishing. Wafer-to-wafer and within wafer grain size variability in the copper film can adversely affect the polish rate of the chemical mechanical processing as well as the ultimate uniformity of the surfaces of the polished copper structures. Large grain size and low variations in grain size in the copper film are very desirable.
The electrical properties of the copper metallization features are also important to the performance of the associated microelectronic device. Such devices may fail if the copper metallization exhibits excessive electromigration that ultimately results in an open or short circuit condition in one or more of the metallization features. One factor that has a very large influence on the electromigration resistance of sub-micron metal lines is the grain size of the deposited metal. This is because grain boundary migration occurs with a much lower activation energy than trans-granular migration.
To achieve the desired electrical characteristics for the copper metallization, the grain structure of each deposited blanket layer is altered through an annealing process. This annealing process is traditionally thought to require the performance of a separate processing step at which the semiconductor wafer is subject to an elevated temperature of about 400 degrees Celsius. The relatively few annealing apparatus that are presently available are generally stand-alone batch units that are often designed for batch processing of wafers disposed in wafer boats.
One single wafer annealing device is disclosed in U.S. Pat. No. 6,136,163 to Cheung. This device includes a chamber that encloses cold plate and a heater plate beneath the cold plate. The heater plate in turn is spaced apart from and surrounds a heater and a lift plate. The lift plate includes support pins that project up though the heater and the heater plate to support a wafer. The support pins can move upwardly to move the wafer near the cold plate and downwardly to move the wafer near or against the heater plate. One potential drawback with this device is that the chamber encloses a large volume which can be expensive and time consuming to fill with purge gas and/or process gas. Another potential drawback is that the heater may not efficiently transfer heat to the heat plate. Still a further drawback is that the heater plate may continue to heat the wafer after the heating phase of the annealing process is complete, and may limit the efficiency of the cold plate.
Another single wafer device directed to the photolithography field is disclosed in U.S. Pat. No. 5,651,823 to Parodi et al. This device includes heating and cooling units in separate chambers to heat and cool photoresist layers. Accordingly, the device may be inadequate and/or too time consuming for use in an annealing process because the wafer must be placed in the heating chamber, then removed from the heating chamber and placed in the cooling chamber for each annealing cycle. Furthermore, the transfer arm that moves the wafer from one chamber to the next will generally not have the same temperature as the wafer when it contacts the wafer, creating a temperature gradient on the wafer that can adversely affect the uniformity of sensitive thermal processes.
The present invention is directed toward apparatuses and methods for processing a microelectronic workpiece at an elevated temperature. An apparatus in accordance with one embodiment of the invention includes a workpiece support positioned to engage and support the microelectronic workpiece during operation. The apparatus can further include a heat source having a solid engaging surface positioned to engage a surface of the microelectronic workpiece. The heat source can further include a heat generator attached directly to and/or integrated with the heat source. At least one of the heat source and the workpiece support is movable relative to the other between a first position with the microelectronic workpiece contacting the engaging surface of the heat source during operation, and a second position with the microelectronic workpiece spaced apart from the engaging surface. The heat source is sized to transfer heat to the microelectronic workpiece at a rate sufficient to thermally process (for example, anneal) a selected material of the microelectronic workpiece when the microelectronic workpiece is engaged with the heat source.
In a further aspect of the invention, the apparatus can include a workpiece support positioned to engage and support the microelectronic substrate, a heat source positioned at least proximate to the workpiece support, and a first heat sink positioned at least proximate to the heat source to cool the heat source. The apparatus can further include a second heat sink positioned at least proximate to the first heat sink to cool the first heat sink. The first heat sink can be movable relative to the heat source and the second heat sink between a first position with the first heat sink engaged with a heat source to cool the heat source, and a second position with the first heat sink engaged with the second heat sink to cool the first heat sink. In a further aspect of this embodiment, the heat source can be positioned above the first heat sink.
In still a further aspect of the invention, a plurality of thermal processing chambers can be positioned one above the other to independently thermally process a plurality of microelectronic workpieces. The thermal processing chambers can have a modular construction such that a lower surface of an upper chamber defines an upper surface of the chamber below.
In yet a further aspect of the invention, the apparatus can include a workpiece support configured to support the microelectronic workpiece and a heat source positioned proximate to the workpiece support. The heat source can have a first region configured to transfer heat to the microelectronic workpiece at a first rate per unit area of the microelectronic workpiece. The heat source can further include a second region configured to transfer heat to the microelectronic workpiece at second rate per unit area of the microelectronic workpiece, with the second rate per unit area being greater than the first rate per unit area. The invention is also directed toward a method for thermally processing a microelectronic workpiece. In one aspect of the invention, the method can include engaging the microelectronic workpiece with a solid heat transfer surface of a heat source, directing heat into the heat source with a heat generator attached directly to and/or integral with the heat source, and transferring heat from the solid surface to the microelectronic workpiece at a rate sufficient to thermally process a selected material of the microelectronic workpiece. The method can further include cooling the microelectronic workpiece and disengaging the microelectronic workpiece from the solid surface.
In a further aspect of the invention, the method can further include at least partially enclosing the microelectronic workpiece by engaging a lid positioned proximate to one side of the microelectronic workpiece with a base supporting the solid heat transfer surface and positioned proximate to an opposite side of the microelectronic workpiece, with the microelectronic workpiece positioned between the lid and the base. The method can further include purging a region adjacent to the microelectronic workpiece of oxidizing agents by supplying a purge fluid to the region. In another aspect of the invention, the method can include transferring heat to one region of the microelectronic workpiece at a different rate per unit area than transferring heat to a second region of the microelectronic workpiece. In still a further aspect of the invention, the method can include heating the solid heat transfer surface with an electrical resistance heater and offsetting a conductive heat loss at a connection terminal of the heater by sizing a connector attached to the terminal to generate electrical resistance heat.
A method in accordance with another aspect of the invention can include forming a plurality of chambers for thermally processing a microelectronic workpiece by providing a first annealing chamber having an first portion, a second portion proximate to the first portion, and a first cavity between the first and second portions. The first cavity is configured to receive a single microelectronic workpiece. The method can further include positioning a third portion proximate to the second portion with the second and third portions defining a second cavity therebetween configured to receive another microelectronic workpiece. The method can still further include disposing a first heat source in the first cavity and disposing a second heat source in the second cavity.